As downward scaling of transistors continues, optimizing power consumption for mobile devices is a major concern. Power consumption consists of two components: dynamic and static. Dynamic (active) power is used while the chip is performing various functions, while static (leakage) power is consumed by leakage current. For both high-performance and low-cost mobile devices developed with deep sub-micron technology, static power has become the major source of total power consumption, primarily due to the transistor's off-state sub-threshold leakage current (Isub). The downward scaling of transistors reduces the transistor's threshold voltage (Vt), which in turn causes an increase in the sub-threshold leakage current (because Isub is an exponential function of Vt). Designers are facing an increased challenge in meeting strict Isub targets.
There are two major leakage reduction techniques currently in use: circuit-based and process-based. The circuit-based technique uses transistor stacking, or multi-threshold voltages. One popular method is a dual-threshold CMOS (complementary metal-oxide semiconductor) that uses high-threshold voltage transistors on non-critical paths to reduce leakage power, and low-threshold transistors on critical paths to maintain circuit performance. Although this technique can be quite effective in reducing sub-threshold leakage current, it adds significant complexity to the process because it requires additional mask steps.
The process-based technique controls the physical dimensions of device components, such as diffusion length or oxide thickness, or introduces mechanical stress in the device's channel and source/drain regions during device fabrication. The presently disclosed technology uses stress-enhancing filler cells to introduce stress in the device's channel region, which can affect the diffusion of pocket ion implants, consequently changing the Vt.